The present invention relates to decoding and reconstruction of two channel MPEG-1 and/or multi-channel MPEG-2 audio data. More specifically, the present invention relates to decoding and reconstruction of MPEG-1 and MPEG-2 audio data using an optimized MPEG subband synthesis algorithm.
Various standards have been developed for the purpose of providing digitally encoded audio data that can be reconstructed to provide good quality audio playback. In the late 1980s, a digital audio/video reconstruction standard known as xe2x80x9cMPEGxe2x80x9d (for Motion Pictures Experts Group) was promulgated by the International Standards Organization (ISO). MPEG syntax provides an efficient way to represent audio and video sequences in the form of compact coded data. MPEG unambiguously defines the form of a compressed bit stream generated for digital audio/video data. Given the knowledge of the MPEG rules, one can thus create a decoder, which reconstructs an audio/video sequence from the compressed bit stream.
MPEG-2 was initiated in the early 1990s to define a syntax for higher quality audio playback for broadcast video. The MPEG-1 audio standard is described in a document entitled xe2x80x9cCoding of Moving Pictures and Associated Audio for Digital Storage Media at up to about 1.5 MBit/sxe2x80x9d (Part 3 Audio) 3-11171 rev 1 (1995) (hereinafter xe2x80x9cthe MPEG-1 Documentxe2x80x9d). The MPEG-2 audio standard is described in a document entitled xe2x80x9cGeneric Coding of Moving Pictures and Associated Audio Informationxe2x80x9d ISO/IEC 13818-3 (1994) (hereinafter xe2x80x9cthe MPEG-2 Documentxe2x80x9d). Both standards documents are incorporated herein by reference for all purposes. Both documents are available from ISO/IEC Case Postale 56, CH-1211, Geneva 20, Switzerland.
The MPEG-2 audio decoding algorithm requires certain steps such as decoding of bit allocation, decoding of scale factors, variable length decoding of audio samples, requantization of samples and subband synthesis. Subband synthesis further requires the steps of matrixing and windowing.
While CPU digital processing power has improved markedly in recent years, the sheer volume of encoded audio/video data that must be rapidly decompressed and played back generally requires some dedicated system hardware, beyond the CPU, for MPEG-2 decoding. CPUs like SPARC from Sun Microsystems, Inc. of Mountain View, Calif., MIPS from Silicon Graphics, Inc. of Mountain View, Calif., Pentium from Intel Corporation of Santa Clara, Calif., etc. can not, in themselves, handle MPEG-2 audio decoding simultaneously with video decoding running at a low system clock. Thus, software/firmware implementation of the MPEG-2 decoding algorithms is not yet practical for mass market consumer applications, and dedicated hardware must be employed to perform at least some MPEG-2 decoding functions.
Although the ISO/MPEG-2 and AC-3 standards do specify the form that encoded audio data must take, they do not specify either the exact sequence of steps or the hardware that must be employed in decoding the data. Thus, designers of MPEG-2 and AC-3 decoding systems are free to provide their own designs for particular applications. In fact, it is expected that each time an MPEG-2 decoder is to be designed for a new application, a designer will generate a new integrated circuit layout for the decoder.
Thus, it would be desirable to find a way to perform a functional partitioning of the MPEG-1, MPEG-2 and AC-3 audio decoding algorithms such that the partitioning allocates some of the decoding steps to be done in hardware and the remaining tasks to be done in firmware. Furthermore, in the implementation of the firmware/hardware partitioning, it is also desirable to optimize audio decoding algorithms, such as those involved during subband synthesis, to speed up decoding of MPEG audio data and reduce the memory, e.g., input RAM, size on chip.
The present invention provides a reusable hardware layout (xe2x80x9ccorexe2x80x9d) for performing some, but not all, MPEG audio decoding functions. The functional blocks comprising this xe2x80x9caudio corexe2x80x9d define a unique hardware architecture which can be used with additional hardware or software for performing those MPEG audio decoding functions not performed by the audio core.
Hereinafter, except where distinctions between the two versions of the MPEG standard exist, the terms xe2x80x9cMPEG-1xe2x80x9d and xe2x80x9cMPEG-2xe2x80x9d will be used interchangeably to reference those audio decoding algorithms promulgated in the original MPEG Document as well as in the MPEG-2 Document, and any future versions of MPEG decoding.
A chip designer may use the audio core of this invention to expedite the designing of an MPEG video decoder. However, because the audio core of this invention performs only some of the MPEG decoding steps, the designer is free to design blocks optimized for the designer""s purposes, to perform the remaining MPEG functions. The audio core of this invention is particularly useful for expeditiously designing xe2x80x9csystemxe2x80x9d chips containing multiple cores on a single chip. Such cores might include, for example, the audio core of this invention, a video core, and a CPU core.
A significant benefit of an audio core derives from its availability for repeated use in many different chips for different applications. In each such chip, the audio decoding functions specified by the audio core can be employed without redesign. Thus, the audio core may be used on a first integrated circuit having a first integrated circuit design and on a second integrated circuit having a second integrated circuit design, with the first and second integrated circuit designs having at least some features not in common. If a system chip is employed, the first integrated circuit design may include a first collection of cores, while the second integrated circuit may include a second collection of cores, etc.xe2x80x94even though the first and second collections of cores have at least one core not in common.
The audio core design itself is preferably stored on a machine readable media such as a magnetic or optical storage unit. The information content of the core preferably includes a series of hardware layouts specifying the locations and features of various circuit elements comprising the audio core architecture. Ultimately, the audio core design is implemented as hardware on one or more chips. Thus, the audio core design exists as both an intangible description of hardware and as the actual hardware itself.
In one embodiment, the audio decoder core design specifies that at least the following MPEG functions are performed by the hardware: sub-band synthesis (or xe2x80x9cmatrixingxe2x80x9d) and windowing. These functions are detailed in the MPEG-1 Document. In especially preferred embodiments, other MPEG-2 functions such as bit allocation decoding, scale factor decoding, variable length decoding, requantization, decoupling, rematrixing, and dynamic range compression are not performed by the audio core of this invention.
Preferably, the control logic unit specifies in which function or group of functions of the MPEG decoding process the audio core currently resides. The control logic unit includes an MPEG state machine for generating MPEG current state (also referred to as xe2x80x9ccurstatexe2x80x9d), secondary state (also referred to as xe2x80x9csecstatexe2x80x9d) and loop count (also referred to as xe2x80x9cloopcntxe2x80x9d), information. This information is employed by the RAM and ROM addressing logic to specify appropriate addresses for reading and writing data.
In one aspect the present invention provides a digital audio decoder. The decoder includes: (i) an audio core which defines hardware for matrixing and windowing during decoding of MPEG digital audio signals such that matrixing coefficients are multiplied by discrete modified sample values during the matrixing operation; (ii) an input RAM coupled to the audio core and configured to store the discrete modified sample values calculated outside the audio core in preparation for the matrixing operation and configured to store intermediate values calculated by the audio core during the matrixing operation that are written back to the input RAM. The modified sample values represent either a summation of two samples of MPEG audio data or a difference of the two samples of MPEG audio data.
The input RAM may be located outside of the audio core. An input RAM interface may control reading of samples from an input data partition of the input RAM and may control writing intermediate values generated during matrixing to one or more intermediate partitions of the input RAM. The input RAM interface may also control reading intermediate values from the input RAM. The matrixing operation may include calculating Vi=xcexa3(Nik)(Sxe2x80x2k), wherein Nik is the matrixing coefficient for i=0 to 63 and k=0 to 31, Sxe2x80x2k is the modified sample value, and for even values of the i of the matrixing coefficient Sxe2x80x2k=Sk+S31xe2x88x92k, where k=0 to 30 and for odd values of i of the matrixing coefficient Sxe2x80x2k=Skxe2x88x92S31xe2x88x92k, where k=1 to 31.
In a preferred embodiment, the input RAM of the present invention may include a samples input RAM and an intermediate values input RAM, which is segregated from the samples input RAM. The samples input RAM and the intermediate values input RAM may be located outside of the audio core. An input RAM interface may control reading of samples from the samples input RAM and may control writing intermediate values generated during matrixing to the intermediate values input RAM. The input RAM interface may also control reading intermediate values from the samples input RAM. The intermediate values input RAM may include one or more partitions to store intermediate values for matrixing during decoding MPEG digital audio signals. The samples input RAM and intermediate values input RAM may be coupled to separate addressing logic.
In another aspect, the present invention provides a process of decoding MPEG digital audio signals in a digital audio decoder including a firmware and a hardware, both of which are configured to decode MPEG audio signals. The process includes: (i) receiving MPEG encoded digital audio signals; (ii) decoding at least partially the digital audio signals by the firmware using MPEG audio algorithms that precede matrixing and windowing; and (iii) generating modified sample values of MPEG audio data by the firmware for matrixing, the modified sample values represent either a summation of two samples of MPEG audio data or a difference of the two samples of MPEG audio data.
The step of decoding using MPEG audio algorithms that precede matrixing may include the steps of decoding, bit allocation, decoding of scale factors and requantization. The decoding process may further include computation of the modified sample values, writing modified sample values by the firmware to a samples input RAM. The further decoding process may further still include performing the matrixing, windowing and downmixing on the modified sample values by the hardware. The matrixing operation may include calculating Vi=xcexa3(Nik)(Sxe2x80x2k), wherein Nik is the matrixing coefficient for i=0 to 63 and k=0 to 31, Sxe2x80x2k is the modified sample value, and for even values of the i of the matrixing coefficient Sxe2x80x2k=Sk+S31xe2x88x92k, where k=0 to 30 and for odd values of i of the matrixing coefficient Sxe2x80x2k=Skxe2x88x92S31xe2x88x92k, where k=1 to 31. Sk represents the original samples which are input to the MPEG sub-band synthesis step.
The firmware may control the operation of a CPU and the hardware may define an audio core. The decoding process may further include: (i) performing downmixing and pulse code modulation by the hardware to produce an output; and (ii) writing the output produced by the hardware to an output RAM. In one embodiment of the present invention, for a period of time the decoding the digital audio signals by the firmware and the performing the windowing and the downmixing by the hardware may be carried out simultaneously.
In the decoding process described above, the step of decoding at least partially the digital audio signals by the firmware may include decoding at least partially audio data for a first channel using MPEG audio algorithms that precede the matrixing to produce values for a first channel that are written to a samples input RAM; and the step of performing the matrixing by the hardware may include performing matrixing on the values for the first channel to compute intermediate values that are written to an intermediate values input RAM. The intermediate values input RAM may be segregated from the samples input RAM. The decoding process may further include signaling the hardware to begin performing matrixing on the values for the first channel, when the firmware concludes writing the values for the first channel to the samples input RAM.
The decoding process may further still include signaling the firmware to begin decoding at least partially audio data for a second channel using MPEG audio algorithms that precede matrixing, when the hardware consumes the modified sample values for the first channel in the input RAM to compute a first set of the intermediate values and completes writing the first set of the intermediate values to the intermediate values input RAM.
The first set of intermediate values may be the intermediate results produced after the hardware completes the matrixing step of decoding MPEG encoded data for the first channel. After decoding is complete, the decoding process may further include: (i) writing by the hardware an output for the first channel to an output RAM after hardware completes decoding the audio data for the first channel and (ii) waiting by the hardware for the firmware to complete writing values for a second channel to the samples input RAM. The number of the modified sample values may be 32. The firmware may compute the modified sample values by using an accumulator that computes a summation of two original samples of MPEG audio data or a difference of the two original samples of MPEG audio data.
In yet another aspect, the present invention provides a process of decoding MPEG digital audio signals. The process includes: (i) receiving modified sample values in a samples input RAM, the modified sample values representing either a summation of two original samples of MPEG audio data or a difference of the two original samples of MPEG audio data; (ii) matrixing the modified samples in an audio core; (iii) writing intermediate values calculated during matrixing to an intermediate values input RAM; and (iv) windowing the intermediate values in the audio core.
The samples input RAM may be segregated from intermediate values input RAM. The step of receiving modified sample values may include receiving modified sample values for a first channel and may further include signaling firmware to begin decoding at least partially audio data for a second channel using MPEG audio algorithms that precede matrixing, when the audio core consumes the modified sample values for the first channel in the input RAM during matrixing to compute a first set of the intermediate results and completes writing the first set of the intermediate results to the intermediate values input RAM.
The first set of intermediate values may be the intermediate values produced after the audio core completes the matrixing step of decoding MPEG encoded data for the first channel. The decoding process, in this embodiment, may further include: (i) writing an output for the first channel to an output RAM after audio core completes decoding the audio data for the first channel; and (ii) waiting for the firmware to complete writing values for a second channel to the samples input RAM. The step of matrixing the modified samples in an audio core may include producing matrixing vector values by multiplying the modified sample values and corresponding matrixing coefficients. The matrixing operation may include calculating Vi=xcexa3(Nik)(Sxe2x80x2k), wherein Nik is the matrixing coefficient for i=0 to 63 and k=0 to 31, Sxe2x80x2k is the modified sample value, and for even values of the i of the matrixing coefficient Sxe2x80x2k=Sk+S31xe2x88x92k, where k=0 to 30 and for odd values of i of the matrixing coefficient Sxe2x80x2k=Skxe2x88x92S31xe2x88x92k, where k=1 to 31. After matrixing, the decoding process may further include: (i) retrieving appropriate values from intermediate values input RAM; and (ii) multiplying the appropriate values by corresponding windowing coefficients.
In yet another aspect, the present invention provides a digital audio decoder. The digital audio decoder includes: (i) means for decoding digital audio signals, which defines hardware for matrixing during decoding MPEG digital audio signal; and (ii) means for storing coupled to the means for decoding digital audio signals and configured to store discrete number of modified sample values that are calculated outside the means for decoding digital audio signals and loaded on the means for storing in preparation for matrixing and configured to store intermediate values that are calculated by the means for decoding digital audio signals during matrixing that are written back to the means for storing, the modified sample values represent either a summation of two samples of MPEG audio data or a difference of the two samples of MPEG audio data.